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The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator

机译:统一累加器架构:可配置,便携式和可扩展的浮点累加器

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Applications accelerated by field-programmable gate arrays (FPGAs) often require pipelined floating-point accumulators with a variety of different trade-offs. Although previous work has introduced numerous floating-point accumulation architectures, few cores are available for public use, which forces designers to use fixed-point implementations or vendor-provided cores that are not portable and are often not optimized for the desired set of trade-offs. In this article, we combine and extend previous floating-point accumulator architectures into a configurable, open-source core, referred to as the unified accumulator architecture (UAA), which enables designers to choose between different trade-offs for different applications. UAA is portable across FPGAs and allows designers to specialize the underlying adder core to take advantage of device-specific optimizations. By providing an extensible, open-source implementation, we hope for the research community to extend the provided core with new architectures and optimizations.
机译:由现场可编程门阵列(FPGA)加速的应用通常需要流水线式浮点累加器,并且需要进行各种折衷。尽管先前的工作介绍了许多浮点累加架构,但很少有内核可供公众使用,这迫使设计人员使用定点实现或供应商提供的内核,这些内核不具有可移植性,并且通常未针对所需的交易集进行优化。断断续续。在本文中,我们将以前的浮点累加器体系结构组合并扩展到一个可配置的开源内核中,该内核称为统一累加器体系结构(UAA),使设计人员可以在针对不同应用的不同折衷之间进行选择。 UAA可跨FPGA移植,使设计人员可以专门化基础加法器内核,以利用特定于器件的优化。通过提供可扩展的开源实现,我们希望研究界可以通过新的体系结构和优化来扩展所提供的核心。

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