基于FPGA的逻辑分析仪SOPC设计

摘要

采用SOPC方法设计了逻辑分析仪,分析了系统中各组成部分的工作原理,重点阐述了利用FPGA片内PLL的时钟分相采样法,将系统采样率提高到400 MSa/s.该设计成本较低,可以满足一般数字电路的调试,具有很好的实用价值.%A logic analyzer is designed by using the SOPC method. The working principle of each part of the system is analyzed. And the sampling method of split phase clock using the PLL in FPGA are especially described. The sampling rate of the system is 400 Msa/s. The system is economical and can satisfy the debugging of the normal digital circuit. It has good practical value.