在晶元级Si衬底上制备高深宽比SiO2周期图形

摘要

本文主要介绍了通过步进式光刻、反相剥离和F基等离子体刻蚀工艺在晶元级Si衬底上制备SiO2图形的过程,在6 in(15．24 cm) Si衬底上实现了均匀的周期分别为1．0μm和1．6μm、深宽比分别为2．3和1．4的SiO2周期性掩膜.尤其在周期为1μm的条件下,窗口通过过曝光和反相剥离工艺减小到330 nm,该尺寸超越了试验用步进式光刻设备的极限精度尺寸.在通过HF 和KOH 溶液处理后,得到了带有V 型槽和较光滑侧壁的SiO2图形的Si衬底,该图形适用于Ⅲ-Ⅴ半导体通过深宽比位错捕获技术的材料生长.这种均匀的晶元级图案制备方案促进了图形化Si衬底技术和Si基Ⅲ-Ⅴ半导体异质外延.%In this paper, the fabrication of SiO2 patterned Si substrate by stepper lithography, lift-off process and F-based plasma etching was demonstrated, by which the SiO2 trenches with periods of 1. 0μm and 1. 6 μm and aspect ratios of 2. 3 and 1. 4 were uniformly formed on a 6 in(15. 24 cm) Si sub-strate. Especially, the opening window for the pattern with period of 1. 0μm was shortened to 330 nm by over-exposure and Al film lift-off, which was beyond the limit of the stepper lithography used in the ex-periment. After further treatment by HF and KOH solutions, the smooth high-aspect-ratio SiO2 trenches were uniformly formed on V-grooved Si substrate, which makes the substrate suitable for theⅢ-Ⅴsemi-conductor through aspect-ratio-trapping technology. Such wafer-scaled uniform fabrication technology can promote the development of patterned Si substrates and Ⅲ-Ⅴ semiconductor hetero-epitaxy on them.