IP核打包及验证方法研究

摘要

IP Core,as the sublimation of IC designs,is the basis for design of very large scale SoC circuits.IP package is one of very important link before IP core is released to users.The formats of IP Core such as coreKit and IP -XAC are flexible.In consideration of the completeness of IP Core,coreKit format is used as an example to make more detailed studies on the method of IP core package and verification by means of coreTools EDA tool.Firstly,for data preparation,two related and auxiliary files i.e.HDL configuration and interface definition are required.Then,the process of packaging,seven steps such as setting up package flow,invoking coreBuilder tool,input setup,memory maps,verification, synthesis setup and package,is described accordingly.Finally,the result of IP core package is verified through IP core release and IP core integration,which proves the correctness and practicability of IP core package.%IP 核是集成电路设计的升华，是超大规模 SoC 电路设计不可或缺的物质基础。IP 核打包是 IP 核发布给用户之前一个非常重要的环节。目前，IP 核的格式比较灵活，有 coreKit、IP －XACT 等。考虑到 IP 核的完整性，以 coreKit 格式为例，借助于 coreTools EDA 工具对 IP 核打包及验证方法进行了较为详细的研究。先从 IP 核的数据准备开始，指出需要提供 HDL 配置和接口定义两个相关的辅助文件；再从打包过程的七个步骤：建立打包流程、启动 coreBuilder 工具、输入设置、存储器映射、验证、综合设置和打包等，对其进行一步一步阐述；最后通过 IP 核发布和 IP 核集成对 IP 核打包的结果加以验证，证明 IP 核包的正确性和实用性。