串行RapidIO是针对高性能嵌入式系统芯片间和板间互连而设计的,是未来十几年中嵌入式系统互连的最佳选择之一.在以RapidIO为接口的SOC设计中,对RapidlO IP核的验证是其基础.基于对RapidIO协议的理解,研究了RapidlOIP核功能验证的方法、验证平台的搭建以及验证侧试过程的实施,提出了虚拟平台验证与FPGA原型验证相结合的验证方法.该验证过程搭建了可靠的验证平台,为RapidlO IP核的可靠工作提供了保证.文中的研究工作,从验证思路和方法上对于类似设计的验证具有一定的参考价值.%Serial RapidIO is designed for the connection among chips of high performance embedded system and that among boards. It is one of the best choices for the interconnection of embedded system in the future. In the SoC design with the RapidIO as its interface, verification for RapidIO core is the foundation. Based on the understanding of RapidIO protocol,take a research of the method of RapidIO core functional verification, the foundation of verification terrace and the implementation of the verification test process, raised the verification method that combined the virtual terrace verification and FPGA archetype verification. This verification process found a dependable verification testbench, guaranteeing the dependable work of RapidIO IP core. For sinilar designed verification, research in this essay has some reference value in mentality and method field of verification.
展开▼
