A current-mode winner-take-all/loser-take-all (WTA/LTA) circuit is presented to improve the calculation speed and precision of dynamic programming (DP) circuit for optimization in network-on-chip. A regenerative circuit is designed to amplify the difference of input currents and to accelerate the comparison, and hence the resolution and speed for current comparison is improved. The output current of the proposed WTA/LTA circuit is selected to reduce the propagation error caused by mismatch, and to improve the precision of output. Simulation results with TSMC 180 nm technology and 1. 3 V power supply show that the proposed WTA/LTA design provides a resolution of 1 nA and a precision of 99. 5% with high speed and low power. Comparisons between an 8-node dynamic programming circuit that uses the proposed circuit as a basic computational unit and an unimproved DP circuit under the same simulation condition show that the computation delay of the former is reduced about 60%, and precision is improved about 80%.%为了提高片上网络中最优化计算的动态规划电路的速度和精确度,提出了一种CMOS电流模式的winner-take-all/loser-take-all(WTA/LTA)电路.该电路设计了一个可再生结构放大输入电流的差距并加速比较,从而提高了电流比较的解析度和速度；使用了输出选择的方式来减小电流镜引起的失配误差,从而改善了输出电流的精确度.采用TSMC 180 nm工艺技术和1.3V工作电压的仿真实验表明,所提出的WTA/LTA电路可以达到1nA的解析度和99.5％的精确度,同时具有高速、低功耗特性.使用该电路作为基本计算单元的八节点动态规划电路,在相同仿真条件下与未改进的动态规划电路相比,计算延迟减小约60％,同时精确度提高约80％.
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