For characteristics of high impact and inertia short flights of shells firing,a missile-borne storage test instrument based on CPLD was proposed to solve the problems that it was difficult to sample at high-speed using a single-chip storage measurement and whose program might run away, and the storage instrument based on ASIC of high cost could not be expand. The instrument used CPLD chip that could be repeatedly erased as the main chip to achieve high-speed sampling and flexible strategy by its internal logic unit It was designed through dormancy to prevent accidental power-ons through parallel to achieve high-rate sampling, through divider to a-chieve 50 k,100 k and 200 K in three frequency options, through counting to achieve 128 K,448 K negative delay optional. The experimental results showed that the tester had flexible operation and high reliability,could met the requirements of Missile-Borne storage test.%针对炮弹发射时的高冲击性及惯性短时飞行特点,以及单片机存储测试仪程序可能跑飞、难以实现高速采样,专用集成电路存储测试仪成本高、不能扩展等问题,提出了基于复杂可编程逻辑器件(CPLD)的弹载存储测试仪.测试仪采用可反复擦写的CPLD芯片作为主控芯片,利用其内部丰富的逻辑单元实现了可高速采样且使用灵活的存储测试方案,设计通过休眠防止误上电；通过并行实现高速率采样,通过分频实现50 kHz、100 kHz和200 kHz三种频率可选；通过计数实现8K×12 bit,448 K×12 bit两种负延迟可选.实验表明:该测试仪操作灵活,可靠性高,满足弹载存储测试在性能方面的要求.
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