可重构Keccak算法设计及FPGA实现

摘要

Based on the analysis of Keccak algorithm, concerning the situation that the existing hardware implementations of Keccak algorithm lack of flexibility and could only support one version, this paper proposed a new reconfigurable Keccak hardware implementation, which could support four versions algorithms. The proposed design achieved 214 MHz clock frequency using 1 607 slices when being ported to Xilinx Virtex-5 FPGA platform. The experimental results show that the proposed design has the advantages of high throughput (9131 Mbps), good flexibility and supporting four versions.%在分析研究Keccak算法的基础上,针对现有Keccak算法的硬件实现方案版本单一,应用不灵活的问题,设计了一种高性能可重构的Keccak算法硬件实现方案.实验结果表明:该方案在Xilinx公司的现场可编程门阵列(FPGA) Virtex-5平台上的时钟频率可达214 MHz,占用1607 slices;该方案具有吞吐量高(9131 Mbps),应用灵活性好,可支持4种不同参数版本的优点.