一种12bit CMOS全差分SAR ADC

摘要

A 12 bit CMOS ful y differential SAR ADC is presented in this paper.The principle and structure of the circuit are analyzed,and the impact of each part of the circuit on the properties of the ADC was mentioned.The new type of DAC_SUB resistor string and self adjusting comparator structure was put forward.The inlfuence of VCM jitter on the circuit was calculated.Based on TSMC 0.18μm 1.8V/3.3V CMOS process,the ful y differential resistor capacitor hybrid structure was adopted in order to realize the ADC circuit design.The device occupied a layout area of 390um×780um.Test results show that under 1 Ms/s sampling rate,when the frequency of input signal is 31.37kHz,the ENOB is 10.76 bit,and the power consumption is about 2mW.%本文设计一种12bit CMOS全差分SAR ADC，分析了其电路原理和结构，阐述各部分电路对ADC性能的影响，提出新型DAC_SUB电阻串和时间自调节比较器结构，并推算VCM抖动对电路的影响。基于TSMC 0.18μm 1.8V/3.3V CMOS工艺，采用全差分阻容混合式结构，实现ADC设计。本设计ADC的核心版图尺寸为390um×780um，测试结果显示，在1MS/s采样率下，当输入信号频率为31.37kHz时，该ADC的ENOB达到10.76Bit，功耗约为2mW。