本文设计与实现了一种专用于加解密流程控制的协处理器。协处理器根据特定的应用需求，自定义了一种精简的8位指令集，同时采用与SoC系统一致的32位数据位宽设计。协处理器采用三级流水线设计，数据旁路的设计解决了流水线中的数据冒险。通过与加解密算法 IP 联合测试仿真，验证了协处理器能够灵活地完成加解密流程控制工作。通过SM1加密实验，证明了协处理器能够提供较主处理器更好的性能，同时释放大量的主处理器资源，显著提高了SoC的性能。最后DC综合结果显示，该协处理器只占用了很小面积。%A coprocessor specially applied for encryption and decryption flow control was designed. According to the specific application requirement, a kind of reduced 8-bit width instruction set was designed with 32-bit data width design compliant to SoC system. The coprocessor adopted 3 stage pipeline design with data bypass design to prevent data hazards. Joint test with secure IPs showed that the coprocessor could control the encryption and decryption flow flexibly. Experiments on SM1 encryption proved that the coprocessor could provide better performance than the main processor and release main processor resources. The Design Compiler synthesis result showed the coprocessor occupied only a small area.
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