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基于过采样 CDR 的4B/5B 编码的设计与实现

     

摘要

为改善 IEEE1394b 串行总线上传输信息的可靠性,满足设计需求的误码率,其关键在于数字通信系统中串行传输数据编码方式的选择。对此,采用4B/5B 编码方式,并给出一种过采样技术的时钟数据恢复的方法对4B/5B 进行编译码。首先对过采样技术的时钟数据恢复方法过程进行讨论,指出恢复数据时钟是设计的难点。在此基础上建立总体设计框架,从而提高数据传输效率。通过应用 Altera 公司 CycloneⅢ系列的 FPGA 芯片,在开发软件 QuartusⅡ上实现4B/5B 编译码仿真。最后给出仿真波形,验证在过采样技术的时钟数据恢复的方法下的编码方式的可实现性和可靠性。%In order to improve the reliability of information transmission on IEEE1394b the serial bus and to meet the error rate of design requirements,the key issue is the selection of serial transmission data encoding mode in a digital communication system.In this regard,we adopted the 4B/5B encoding mode,and presented a clock data recovery method of oversampling technology for 4B/5B encoding and decoding.First,we discussed the process of clock data recovery method of oversampling,and pointed out that the difficulty in design is to recover data clock,and then constructed the overall design framework on this basis,thereby improved data transmission efficiency.By applying the FPGA chip of Altera Corporation Cyclone Ⅲ series,we implemented the simulation of 4B/5B coding and decoding using development software quartusⅡ.Finally we gave the simulation waveform,and demonstrated the realisability and reliability of the encoding mode in clock data recovery method of oversampling technology.

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