通用可编程LDPC编码器的设计

摘要

基于灵活性和通用性的考虑,设计一种基于多指令、多数据流的可编程处理器结构,实现准循环低密度奇偶校验码(LDPC)的编码算法.与传统的LDPC编码器相比,处理器采用数据位拼接方式实现矩阵与向量相乘,可以获得较高的计算速度、易于芯片布局.目前已经用硬件描述语言在Xilinx ISE平台可编程门阵列芯片XC2VP20上仿真实现了该处理器的架构,最大时钟频率为75 MHz.实验结果表明,该结构适用于多标准的LDPC编码器.%Based on flexibility and versatility, a programmable processor architecture based on multiple instruction and multiple data streams is designed to realize the coding algorithm of quasi cyclic low density parity check codes (LDPC).Compared with the traditional LDPC encoder, the processor uses data bits mosaic method to achieve the matrix and vector multiplication, which can obtain a higher speed and chip layout.Currently processor architecture has been simulated in the ISE Field-Programmable Gate Array (FPGA) platform with Xilinx XC2VP20 chip.The maximum clock frequency is 75 MHz.The experimental results show that the proposed structure is suitable for Multi-standard LDPC encoder.