基于BoothCSD混合编码的模2n+1乘法器的设计

摘要

在余数系统的设计中，模加法器和模乘法器的设计处于核心地位，尤其是模乘法器的性能，是衡量余数系统系能的主要标志之一。文中先推导出Booth编码下的模2 n+1乘法器设计的算法，然后针对Booth编码模乘法器设计中译码电路复杂的问题，提出了一种基于Booth/CSD混合编码的模乘法器设计方法，基于Booth/CSD编码的模乘法器部分积的位宽相对传统的Booth编码乘法器而言，减少了50%；经试验证明，与传统的基-Booth编码的模乘法器相比这种混合编码的模乘法器的速度提高了5%，面积减少24.7%。%In the design of RNS system the designs of,the modulo multiplier and adder are in a core position,espically the performance of the modulo mulitipliers,which is the main mark of a successfully RNS system. In this paper,we deduce the arithmetic used in the design of the Booth-based modulo multiplier first,and then in order to solve the problem of complex decoding circuit in design,we put forward a new method,in which we bring the efficient CSD enconding technology and radix-booth encoding techniques together, the partial product of Booth/CSD encoding module multiplier has a decrease of fifty percent compared with traditional Booth based module multiplier;the test results demonstrate that,in comparision with the traditional Booth based module multiplier the speed which we take Booth/CSD encoding method has an increase of five percent and the area has a decrease of twenty four point seven.