A high speed modulo (2n ? 2p + 1) multiplier design

摘要

References(10) In this express, an optimized architecture for modulo (2n ? 2p + 1) multipliers is proposed. Compared with the state-of-art, synthesized results demonstrate that the proposed multipliers can achieve an average delay savings of about 11.8%. With the increase of n, the average delay savings also increases remarkably.