Sparse hierarchical model order reduction for high speed interconnects.

摘要

The trend of increasing operating frequency and decreasing device size is pushing the complexity of circuit designs to the next level. At high frequency end, interconnect effects give rise to a variety of signal integrity issues. Any overlooked signal integrity issues could be vital and lead to design failures. Significant efforts were devoted to developing interconnect modeling techniques. Sophisticated modeling techniques typically result in large macromodels. In order to lower iterative design cost and deliver inspired designs to the market in time, model order reduction (MOR) techniques were widely adopted by advanced design automation tools.;In this thesis, a novel hierarchical model order reduction technique is proposed. Using this technique, the overall circuit matrices are very sparse after each level of reduction. The technique also introduces an important transformation mechanism for the preservation of moments and passivity. The proposed technique significantly speeds up the order reduction process and is a major contribution to multi-level interconnect circuit simulation.