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CMOS-compatible high voltage integrated circuits.

机译:CMOS兼容高压集成电路。

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Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated.; The high-voltage capabilities of an existing 5 {dollar}mu{dollar}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 V and 190 V respectively, have been fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed and their accuracy verified by comparison with the experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices.; A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. The device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in the current density compared to the lateral DMOS transistor. A simple technique to improve the breakdown voltage and the switching speed of the IBT, without significantly compromising its current carrying capability, is also presented.; In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed. High-voltage lateral DMOS transistors and merged MOS-bipolar devices such as the LIGT and IBT with breakdown voltages of 400 V, have been fabricated using this process. The IBTs, which in addition to having high breakdown voltages have high current handling capabilities as well as high switching speeds, offer better performance than the LIGTs. In addition, the IBT, because it doesn't latch-up, is a more reliable device than the LIGT.; The processes and devices developed in this work have potential applications in the telecommunications and display driver fields.
机译:如果在现有的低压工艺中制造高压IC(HVIC),则可以节省大量成本并缩短开发时间。本文研究了在标准CMOS工艺中制造HVIC的可行性。首先研究了现有的5μmCMOS工艺的高压能力。已经制造出击穿电压分别为50 V和190 V的高压n沟道晶体管和p沟道晶体管,而对所考虑的工艺没有任何修改。开发了这些晶体管的SPICE模型,并通过与实验结果进行比较来验证其准确性。此外,还检查了互连金属化对这些设备的高压性能的影响。多晶硅场板被发现可有效防止这些器件中过早的互连引起的击穿。提出并实现了一种新颖的高压晶体管结构,即基于合并的MOS双极概念的绝缘基极晶体管(IBT)。可以使用标准CMOS工艺实现的器件能够处理高电流密度而不会发生闩锁。与横向DMOS晶体管相比,IBT的电流密度增加了五倍。还提出了一种在不显着损害其电流承载能力的情况下提高IBT击穿电压和开关速度的简单技术。为了增强高压设备的能力,开发了一种使用结隔离的改进的CMOS兼容HVIC工艺。使用该工艺已经制造出高压侧向DMOS晶体管和合并的MOS双极器件,例如击穿电压为400 V的LIGT和IBT。 IBT除具有高击穿电压外,还具有高电流处理能力和高开关速度,其性能优于LIGT。另外,由于IBT不会闭锁,因此它是比LIGT更可靠的设备。在这项工作中开发的过程和设备在电信和显示驱动器领域具有潜在的应用。

著录项

  • 作者

    Parpia, Zahir.;

  • 作者单位

    University of Toronto (Canada).;

  • 授予单位 University of Toronto (Canada).;
  • 学科 Physics Electricity and Magnetism.
  • 学位 Ph.D.
  • 年度 1988
  • 页码
  • 总页数
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 电磁学、电动力学;
  • 关键词

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