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Advanced mobility models for design and simulation of deep submicrometer MOSFETs.

机译:用于设计和仿真深亚微米MOSFET的高级迁移率模型。

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摘要

Carrier mobility is one of the most important parameters affecting the I-V characteristics of MOSFETs. Hence, accurate mobility models that account for all the important scattering mechanisms are an essential requirement for predictive MOS device simulation. This dissertation focuses on issues related to mobility modeling in MOSFETs as they scale to deep submicron dimensions. A new physically-based mobility model for two dimensional (2D) device simulation is presented that accurately models MOSFETs for all channel lengths down to 0.25;Traditionally, channel resistance has been the dominant factor limiting current transport in MOSFETs. However, in deep submicron MOSFETs with lightly-doped drain (LDD) structures, channel resistance has become comparable to the parasitic series resistance, a major component of which comes from the accumulation layer in the LDD region. A unified mobility model is presented that is applicable in both inversion and accumulation layers. A systematic methodology is presented for the calibration and validation of the new model with experimental data. Broad applicability of the new model is established with excellent agreement over a wide range of operating conditions (subthreshold, linear, and saturation) for gate lengths ranging from 20.0;As MOSFETs scale to shorter channel lengths, channel doping levels increase in order to suppress undesirable short-channel effects such as punchthrough and drain-induced barrier lowering (DIBL). One direct consequence of increased doping is enhanced impurity scattering, the importance of which in scaled MOSFETs is established by demonstrating its impact on critical design parameters such as threshold voltage and off-state leakage current. An accurate model for impurity scattering has been developed that, for the first time, properly accounts for 2D confinement and quantum mechanical effects in the inversion layer. A systematic methodology for extracting Coulombic mobility from I-V data is also presented. Based on this scheme, it is shown that in regimes where three dimensional (3D) models grossly over-predict mobility, the new 2D model demonstrates its broad applicability by accurately reproducing experimental results over a wide range of channel dopings, substrate biases, and electron concentrations.
机译:载流子迁移率是影响MOSFET I-V特性的最重要参数之一。因此,考虑所有重要散射机制的精确迁移率模型是预测MOS器件仿真的基本要求。本文主要研究与MOSFET迁移率建模有关的问题,因为它们会扩展到深亚微米尺寸。提出了一种用于二维(2D)器件仿真的新的基于物理的迁移率模型,该模型可以为0.25至0.25的所有沟道长度精确建模MOSFET;传统上,沟道电阻已成为限制MOSFET中电流传输的主要因素。但是,在具有轻掺杂漏极(LDD)结构的深亚微米MOSFET中,沟道电阻已变得可与寄生串联电阻相提并论,其主要成分来自LDD区域中的累积层。提出了适用于反演和累加层的统一移动性模型。提出了一种系统的方法,用于利用实验数据对新模型进行校准和验证。新模型具有广泛的适用性,并且在20.0的栅极长度的广泛操作条件(亚阈值,线性和饱和)范围内达成了出色的协议;随着MOSFET扩展到更短的沟道长度,沟道掺杂水平也随之增加,以抑制不良情况短通道效应,例如击穿和漏极引起的势垒降低(DIBL)。掺杂增加的直接结果是杂质扩散增强,其在规模化MOSFET中的重要性通过证明其对关键设计参数(例如阈值电压和截止态泄漏电流)的影响来确定。已开发出一种精确的杂质散射模型,该模型首次适当地说明了反型层中的二维限制和量子力学效应。还提出了从I-V数据中提取库仑迁移率的系统方法。基于此方案,表明在三维(3D)模型严重高估了迁移率的情况下,新的2D模型通过准确地再现各种沟道掺杂,衬底偏置和电子的实验结果,证明了其广泛的适用性。浓度。

著录项

  • 作者

    Mujtaba, Syed Aon.;

  • 作者单位

    Stanford University.;

  • 授予单位 Stanford University.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 1996
  • 页码 153 p.
  • 总页数 153
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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