Exploiting temporal independence for parallel, distributed, asynchronous, preemptive event-driven simulation of VHDL digital circuit descriptions.

摘要

Concurrent event-driven simulation of digital circuits is essential in reducing simulation time in the verification of large circuit designs. Whereas the concurrent simulation of combinational circuits is relatively straight-forward, realizing conservative, deadlock-free simulation of cyclic designs is difficult. This thesis addresses this challenge by exploiting the temporal independence that arises between dependent components during simulation. Our algorithm {dollar}Psp2EDAS,{dollar} is implemented on both shared memory multiprocessors and distributed environments and is shown to be deadlock-free. We demonstrate its applicability to an existing large body of circuit simulation problems by applying the algorithm to the simulation of VHDL circuit descriptions. Results show that {dollar}Psp2EDAS{dollar} identifies an average of three times as many circuit components concurrently executing per simulation cycle as that exposed by a capable central queue event-driven simulation algorithm.; Our research revealed a significant weakness in VHDL's ability to correctly represent and simulate transmission line interconnects. A discrete model and event-driven simulation algorithm for transmission lines is developed. Also, extensions are proposed to the VHDL grammar and its transport delay timing semantics for using the model. The grammar extensions allows easy and efficient representation of arbitrary interconnect. The simulation algorithm handles both reflective and incident switching transmission line designs. Simulation of PCI, Wired-OR and Ethernet bus are demonstrated. The results affirm the validity and correctness of the solution and shows that the algorithm gives speedups of over 600 times as fast as simulation done with SPICE.