Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling

摘要

As the complexity of microelectronic systems continuously increases, it becomes critical to develop effective tools that can cut the design time and improve the quality of design. DoD needs to develop new tools to be able to simulate large complex systems, and to fully maximize the rapid progress in high performance computing technology occurring today. The goal of this project was to develop and implement efficient paradigms for VHDL simulation on massively parallel processor machines so that we can achieve speed up of up to a hundred times compared to sequential simulation. Our research focus was on performance and behavioral level simulation. The performance model allows us to find the trade off between various hardware components and architectures. Behavioral simulations are used to prove the functional correctness of the system. The research issues involved in the project were: processor communications, synchronization, and event queue manipulation, deadlock handling, communication latency hiding, and granularity of computation. We have measured the performance of the proposed techniques on various platforms such as the IBM SP2 and SGI origin 2000, and achieved speed ups of 31 times.