Design and implementation of low-power ASIC components.

摘要

Wireless communications systems, including third generation cellular radio systems and wireless LANs, have become tremendously popular in recent years. These systems can be implemented using various platforms: Application Specific Integrated Circuit (ASIC), digital signal processor, general purpose processor, and FPGA. This thesis presents our research practices in implementing some of the communication and digital signal processing functions using ASICs.; Low power high speed circuits are highly desirable in wireless communications systems. At the circuit layout level, we illustrate a layout design methodology to improve the performance of final laid-out full adder circuits. At the circuit schematic level, we have proposed a number of low power 4-transistor XOR/XNOR gates as well as a set of full adder circuits, essential to many digital systems such as ALUs, filter banks, and parity checkers, etc. We have also conducted a comprehensive performance study comparing our newly proposed full adder circuits with over 30 other published adders. Results of this study are very important to those building large digital systems, such as low power multipliers. At the algorithm and architecture levels, we propose an area-efficient low power architecture for a mutiplexer-based multiplier. We also propose two algorithms to calculate the output probability of a Boolean function. This probability is essential for power estimation requirement at low power VLSI designs.