We present a novel diffuse interface model for simulating failures due to electromigration and stress induced void evolution in interconnect lines. The model simulates the growth, shape change and migration of voids due to a complex coupling of diffusion along the void surfaces and diffusion through the bulk of the interconnect line. The numerical difficulties associated with conventional sharp interface models in handling complex topology changes as voids evolve, are mitigated by the introduction of a smooth order parameter field to describe void structure. The order parameter takes on distinct uniform values within the material and the void, varying rapidly from one to the other over narrow interfacial layers associated with the void surface. Field equations governing the evolution of the order parameter, to simulate surface diffusion, and the diffusion of vacancies through the bulk, under the coupled effects of stresses and the “electron wind” force, are derived. Asymptotic analyses of these equations are performed to demonstrate the desired correspondence between the sharp and the diffuse interface models in the limit of vanishing interface thickness. In particular, the zero contour of the order parameter is shown to track the motion of the evolving void surface. Finite element schemes used to solve the field equations governing the evolution of the order parameter, the vacancy concentration, the electric potential and the stress in the interconnect line are also discussed. The capabilities of the diffuse interface model are demonstrated by applying it to simulate a range of problems involving void growth, shape change and migration, break-up and coalescence of voids, void healing and buildup and relaxation of stresses in the interconnect line. Results obtained are compared with void morphologies observed experimentally in real interconnect structures. The diffuse interface model can be easily extended to handle complex void topology changes in three dimensions, making it a potentially powerful tool for simulating realistic failures of microelectronic interconnect lines.
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