Developpement et caracterisation d'un procede de fabrication 0.8 micron CMOS sur substrat SOI (French text).

摘要

This thesis presents the design, the development and the implementation of a CMOS process adapted to an SOI substrate, the fabrication of the two types of MOSFET (n-channel and p-channel) and their electrical characterization. The success of these processing steps, and the comparison of the results with equivalent MOSFET fabricated on bulk substrates, allow us to assess the full benefit of this SOI technology.; The first stage of this project was concentrated on the choice of the SOI starting material and the design and development of the process itself. The semiconductor process and device simulation tools were extremely helpful in the success of this part. Some exploratory silicon lots were manufactured during this phase to adjust the various SOI process parameters. The second phase was targeted towards the development of a self-aligned silicide process, which needed to be fully compatible with the global SOI process. Two complete lots, using the final SOI starting material selected, were then manufactured.; Finally, the last phase of this project was completely dedicated to the electrical characterization of the manufactured devices. (Abstract shortened by UMI.)