Transmission gate technique for soft error mitigation in nanometer CMOS circuits.

摘要

Due to scaling of feature size, increased clock frequencies and reduced power supply, Soft Error induced by Single Event Effects (SEEs) became common to the CMOS intergraded circuit. The normal functioning of a circuit without radiation protection will be seriously disturbed.;This work studies 65nm CMOS SEEs filters based on transmission gate techniques. The transmission gate can be hardened against SEEs if its gate voltages are varied. The one, two and four-stage transmission gate based mitigation circuits are proposed and evaluated.;Although increasing propagation delay, adding more stages of transmission gate and applying the varied gate voltage VN=VP=0.6V can improve radiation tolerance of the mitigation circuit. For glitch charge larger than 150fC, the four-stage method performs better than other approaches; for the glitch charge less than 150fC, the one-stage method performs better than other approaches.;The propagation delay of a transmission gate increases with its aspect ratio decreasing and size increasing. Besides, adding more stages of transmission gate can increase propagation delay of the mitigation circuit. And applying varied gate voltage VN=VP=0.6V brings about 250% to 350% more propagation delay than normal gate voltage.;Compared to the conventional driver sizing and emerging TTF method, varied gate voltage transmission gate technique successfully reduces glitch sensitivity and area penalty of circuits, but produce large propagation delay.