Design and implementation of an efficient multiphase digital pulse width modulator with integrated graphical display processor using FPGA.

摘要

Field Programmable Gate Arrays (FPGAs) play a very important role in modern worlds digital system design and architecture. One of the most important advantage of FPGAs is that they are reconfigurable (i.e.) they allow the user to reconfigure the integrated circuit any number of times as per the requirements, after manufacturing. FPGAs are increasingly becoming the choice for the applications involving, high speed and high performance computing. Pulse Width Modulation is one of such applications which mostly involves power delivery and voltage regulation. Thus for effective management of power consumed by the device and reduction in power loss there is a need for high resolution pulse width modulators.;This research focuses on designing and implementing an effective digital pulse width modulator which offers very high resolution, using a CYCLONE II EP2C35F6 72C6 FPGA device. This research offers a compromise solution between the area, clock frequency and resolution which were important issues in traditional methods, and also provides an optimized design removing several overheads which were present in some of the previous research.;This research also involves the design and implementation of a graphical display processor which is used to graphically observe and verify the pulse width modulated signals generated by the DPWM, eliminating the need to use traditional devices like oscilloscopes, logic analyzers etc. The graphical display processor proposed in this research work offers a compromise solution for functional flexibility and hardware reconfigurability, which is used to display and manipulate the signals in an effective way.