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Timing optimization for nano-meter VLSI designs.

机译:纳米级VLSI设计的时序优化。

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In nanometer technology, designers face many challenges to meet timing constraints. Three of those critical challenges are power noise, process variation, and interconnect delay. In this dissertation, we will review these challenges and also propose our solutions.; Power noise leads to IR-drop, which can affect chip timing and even functionality. To overcome the power noise problem, we propose a power-noise-reduction flow. There are two steps in the flow---prediction and correction. Prediction is done before placement to estimate decoupling-capacitance (decap) requirements for each cell. Correction is a new post-layout gate-sizing algorithm that considers power noise and timing constraints.; Because of the lithography challenges and ever-shrinking device sizes, process variation leads to uncertainty of chip performance. Some ways to adjust the chip performance after fabrication will be very useful to reduce the process variation effects. We propose a new clock architecture for FPGAs with the advantageous feature that clock skew is field-programmable. We can adjust the clock skew to achieve our timing constraints. We also propose algorithms that can conduct clock scheduling efficiently.; Although the gate delay shrinks as the technology advances, the interconnect delay does not shrink accordingly. The increased coupling capacitance and interconnect resistance keep the interconnect delay high. To tackle this interconnect-delay problem we need a better delay-budgeting algorithm that can explore various means for improvement. We propose an algorithm that combines the advantage of retiming with delay budgeting to help us achieve timing goals.; The challenges for nanometer designs are daunting. Many nanometer effects have great impact on circuit timing. We need to rely on continuous innovation to keep in step with the rapid advances. In this dissertation, we propose three techniques to answer some nanometer challenges. Our experiments have shown that these techniques are efficient and produce good results.
机译:在纳米技术中,设计师要满足时序约束面临许多挑战。这些关键挑战中的三个是电源噪声,工艺变化和互连延迟。在本文中,我们将回顾这些挑战并提出解决方案。电源噪声会导致IR下降,从而影响芯片时序甚至功能。为了克服电源噪声问题,我们提出了一种降低功率噪声的流程。流程分为两个步骤-预测和校正。在放置之前进行预测以估计每个单元的去耦电容(decap)要求。校正是一种新的布局后选通算法,该算法考虑了电源噪声和时序约束。由于光刻挑战和不断缩小的器件尺寸,工艺变化导致芯片性能不确定。在制造后调整芯片性能的一些方法对于减少工艺变化的影响非常有用。我们为FPGA提出了一种新的时钟架构,其优势在于时钟偏斜是可现场编程的。我们可以调整时钟偏斜以实现我们的时序约束。我们还提出了可以有效进行时钟调度的算法。尽管随着技术的发展,栅极延迟会减小,但互连延迟不会相应地减小。增加的耦合电容和互连电阻使互连延迟较高。为了解决此互连延迟问题,我们需要一种更好的延迟预算算法,该算法可以探索各种改进方法。我们提出了一种结合重定时和延迟预算优势的算法,以帮助我们实现时序目标。纳米设计面临的挑战令人生畏。许多纳米效应对电路时序有很大影响。我们需要依靠不断的创新来跟上快速发展的步伐。本文提出了三种解决纳米挑战的技术。我们的实验表明,这些技术有效且产生了良好的效果。

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