Impact of Supply Noise on Nano-Meter VLSI Design: Hard or Soft Threshold?

摘要

With VLSI keeps scaling down, power supply noise margin gets further diminished due to the relatively stable threshold voltage. On the other hand, the continuously growing current density incurs additional supply noise, which easily violates the pre-set power integrity noise margin threshold. Thus, power integrity (PI) designers have to either conduct repeated back-tracking or add additional die area to reduce the unwanted supply noise, which is both cost and time consuming. A very natural question that may arise is then what happens if this noise margin threshold is violated? In this paper, we will investigate the impact of supply noise on various designs for nano-meter VLSI and discuss the potential opportunities that may provide PI designers with additional design flexibility.