METHOD FOR TIMING STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUITS

摘要

PURPOSE: A method for timing statistical timing optimization of VLSI circuits is provided to define TYC(Timing Yield Criticality) and calculate the TYC based on the definition. CONSTITUTION: ADD and MAX calculations of a block-based SSTA(Statistical Static Timing Analysis) method are linearly approximated(330). Jacobian matrixes between nodes are generated as matrix configuration elements which are configured with differential coefficients calculated in a linear approximation process(340). The Jacobian matrixes are propagated as virtual source nodes in a virtual sync node(350), and the changed arrival time values of the circuit are calculated. Calculated is a TYC(Timing Yield Criticality) which is a variable of the circuit timing yield caused by the fine variation of the average arrival time for each node.