首页> 外文学位 >High growth rate and high purity semi-insulating epitaxy using dichlorosilane for power devices.
【24h】

High growth rate and high purity semi-insulating epitaxy using dichlorosilane for power devices.

机译:使用二氯硅烷的高生长速率和高纯度半绝缘外延,用于功率器件。

获取原文
获取原文并翻译 | 示例

摘要

Silicon Carbide (SiC) has long been considered a material of choice for high power and high frequency devices due to its wide band gap, high breakdown field, and high thermal conductivity. Chemical vapor deposition (CVD) of 4H-SiC using silane (SiH4) and light hydrocarbons e.g. propane (C3H8) or ethylene (C2H4) is the standard technology of growing epitaxial layers for any device applications. For high-voltage (>10 kV) devices made of SiC thick (>100 mum), low doped (~2x1014 cm -3) epilayers are needed. To obtain such thickness with standard silane-based CVD process, which have growth rates of 6-7 um/hr, process times would typically exceed ten hours, leading to a significant increase in the manufacturing cost. Growth rates higher than the usual may be achieved by increasing precursor flow, this typically leads to homogeneous nucleation of liquid silicon droplets, eventually decreasing the efficiency of precursor use and degrading crystal quality.;Due to its unique material properties, SiC has great potential to replace conventional semiconductors in high frequency applications. Semi-insulating (SI) epitaxial layers are required to achieve this. Most common method for introducing the SI property to the substrate is to use vanadium as a deep level dopant to pin the Fermi level near the mid-bandgap. Although this is the original conceived method for producing commercial SI substrates, reports indicate that vanadium degrades crystal quality as indicated by increased FWHM of X-ray diffraction rocking curve.;In this dissertation both of the above mentioned problems are addressed. Thick (100 mum), high quality low doped (~2x1014 cm -3) 4H-SiC epilayers have been grown in a vertical hot-wall chemical vapor deposition system at a high growth rate (50--100 mum/hr) on (0001) 80 off-axis substrates. Novel precursor Dichlorosilane (SiH2Cl2) is used as Siprecursor, using the idea that the silicon droplets can be dissolved by the presence of species that bind stronger to silicon than silicon itself. X-ray rocking curves indicate that the epilayers were of high crystallinity, with linewidths as narrow as 7.8 arcsec being observed, while microwave photoconductive decay (iPCD) measurements indicated that these films had high injection (ambipolar) carrier lifetimes in the range of 2 mus. These films also appeared to be free of polytype inclusions.;Thick high purity semi-insulating (SI) homoepitaxial layers on Si-face 4H-SiC have been grown systematically, with resistivity ≥ 109 O-cm. This is done by maintaining high C/Si ratio during chemical vapor deposition over a relatively wide C/Si ratio window (1.3-1.5). A reconciliation of impurity concentration with measured resistivity indicated a compensating trap concentration of ~1015 cm-3 present in the SI-epilayer, and is supported by quenched photoluminescence lifetimes. High resolution photo-induced transient spectroscopy (HRPITS) analysis identified these traps as Si-vacancy related deep defect centers, with no detectable EH6/7 and Z 1/2 levels, consistent with the higher C/Si ratio. A recombination lifetime of ~5ns suggests application in fast-switching power devices.
机译:碳化硅(SiC)因其宽带隙,高击穿场和高导热性而长期以来被认为是大功率和高频设备的首选材料。使用硅烷(SiH4)和轻烃(例如,碳酸氢钠)进行4H-SiC的化学气相沉积(CVD)。丙烷(C3H8)或乙烯(C2H4)是用于任何设备应用的生长外延层的标准技术。对于由SiC厚(> 100微米)制成的高压(> 10 kV)器件,需要低掺杂(〜2x1014 cm -3)外延层。为了通过具有6-7um / hr的生长速率的标准的基于硅烷的CVD工艺来获得这种厚度,工艺时间通常将超过十小时,从而导致制造成本的显着增加。通过增加前驱物流量可以实现比通常水平更高的生长速率,这通常会导致液态硅滴均匀成核,最终降低前驱物使用效率并降低晶体质量。;由于其独特的材料特性,SiC具有很大的潜力替代高频应用中的常规半导体。为此需要半绝缘(SI)外延层。将SI特性引入衬底的最常见方法是使用钒作为深能级掺杂剂,将费米能级固定在中带隙附近。尽管这是生产工业SI衬底的最初构想方法,但报告表明,钒会降低晶体质量,这是由X射线衍射摇摆曲线的FWHM增大所表明的。在本文中,解决了上述两个问题。厚(100 mum),高质量,低掺杂(〜2x1014 cm -3)4H-SiC外延层已在垂直热壁化学气相沉积系统中以高生长速率(50--100 mum / hr)生长在( 0001)80个离轴基板。新型前驱体二氯硅烷(SiH2Cl2)用作Siprecursor,其思想是可以通过存在与硅结合的物种比与硅本身结合更强的物质来溶解硅滴。 X射线摇摆曲线表明外延层具有高结晶度,观察到的线宽窄至7.8 arcsec,而微波光导衰减(iPCD)测量表明这些膜具有2微米范围内的高注入(双极性)载流子寿命。这些膜似乎也没有多型夹杂物。系统地生长了Si面4H-SiC上的厚高纯度半绝缘(SI)同质外延层,电阻率≥109 O-cm。这是通过在相对较宽的C / Si比窗口(1.3-1.5)上在化学气相沉积过程中保持高C / Si比来完成的。杂质浓度与测得的电阻率的调节表明,在SI外延层中存在〜1015 cm-3的补偿阱浓度,并由淬灭的光致发光寿命支持。高分辨率光诱导瞬态光谱法(HRPITS)分析确定这些陷阱为与硅空位有关的深缺陷中心,没有可检测的EH6 / 7和Z 1/2含量,与较高的C / Si比一致。约5ns的重组寿命表明该器件可用于快速开关功率器件。

著录项

  • 作者

    Chowdhury, Iftekhar.;

  • 作者单位

    University of South Carolina.;

  • 授予单位 University of South Carolina.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 169 p.
  • 总页数 169
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

  • 入库时间 2022-08-17 11:37:08

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号