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High Purity Semi-Insulating 4H-SiC Epitaxial Layers by Defect-Competition Epitaxy:Controlling Si Vacancies

机译:缺陷竞争外延的高纯度半绝缘4H-SiC外延层:控制硅空位

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摘要

Thick, high-purity semi-insulating (SI) homoepitaxial layers on 4H-SiC were demonstrated using a novel compensation scheme controlled by defect-competition epitaxy at C/Si ratios of 1.3-1.5. These showed resistivity of ~10~9 Ω cm. Comparison of secondary ion mass spectra between low-doped epilayers grown at C/Si ratio <1.3 and SI epilayers grown at C/Si ratio >1.3 showed little difference in residual impurity concentrations. A reconciliation of impurity concentration with measured resistivity indicated a compensating trap concentration of ~10~(15) cm~(-3) present only in SI epilayers. High-resolution photoinduced transient spectroscopy (HRPITS) identified them as Si vacancy related centers, with no detectable EH_(6/7) and Z_(1/2) levels. Recombination lifetimes of ~5ns suggest application in fast-switching power devices.
机译:使用一种由缺陷竞争外延在C / Si比为1.3-1.5的情况下控制的新颖补偿方案,证明了4H-SiC上的厚,高纯度半绝缘(SI)同质外延层。这些显示出〜10〜9Ωcm的电阻率。比较以C / Si比<1.3生长的低掺杂外延层和以C / Si比> 1.3生长的SI外延层的二次离子质谱,发现残留杂质浓度差异很小。杂质浓度与测得的电阻率的调节表明,仅在SI外延层中存在〜10〜(15)cm〜(-3)的补偿陷阱浓度。高分辨率光致瞬态光谱法(HRPITS)将其确定为与硅空位相关的中心,没有可检测的EH_(6/7)和Z_(1/2)水平。约5ns的重组寿命建议应用在快速开关功率器件中。

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  • 来源
    《》 |2012年第2期|p.025502.1-025502.3|共3页
  • 作者单位

    University of South Carolina, Electrical Engineering, Columbia, SC 29208, U.S.A.;

    University of South Carolina, Electrical Engineering, Columbia, SC 29208, U.S.A.;

    Institute of Electronic Materials Technology, 01-919 Warsaw, Poland;

    Institute of Electronic Materials Technology, 01-919 Warsaw, Poland;

    Naval Research Laboratory, Washington, D.C., U.S.A.;

    University of South Carolina, Electrical Engineering, Columbia, SC 29208, U.S.A.;

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