Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as Land Grid Array (LGA) and Quad-Flat No-Lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The goal of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations. Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed in order to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using Solder Paste Inspection (SPI) system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated Thermal Cycling (ATC) was used to determine the reliability of the solder joints. For the LGAs, solder joints formed with higher paste volume survived longer in ATC compared to lower volume joints. Low solder paste volume deposits did not affect BGA devices in ATC. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA, QFN and BGA devices. This research provides valuable data because, very little data is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use +/-50% of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.
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