Backside thinning and processing for through-silicon via (TSV) technology.

摘要

This research was performed to create through-silicon vias (TSVs) for chip stacking applications. This thesis discusses three of the processing steps involved in producing through-silicon vias; wafer bonding, wafer thinning, and exposing blind vias from the back side. Wafer bonding involves the attachment of a process wafer to a carrier wafer that acts as a handling wafer for support as the process wafer is thinned to a final thickness of ∼100 mum. The various bonding techniques that have been attempted involve the use of liquid crystal polymer (LCP), GenTak adhesive, and Al high temperature controlled release tape. Wafer thinning is performed using two steps for material removal. Mechanical grinding performs the bulk of the removal. The process wafer is thinned to approximately 105 mum or until the photolithographic alignment marks become visible on the back side of the wafer. After exposing the alignment marks, the wafer is mechanically polished to remove the damage that is done during back grinding to provide a smooth and planar surface for processing. Next, to expose the vias from the back side, reactive ion etching (RIE) is used in conjunction with a photoresist mask to selectively etch silicon in the areas above the via. This leaves the process wafer at the same overall thickness of 105 mum, but exposes the vias from the back side to enable the completion of a TSV.