Materials and electrical properties of ALD zirconium dioxide gate dielectrics.

摘要

For several decades, transistor dimensions including gate dielectric thickness have been reduced in order to continually increase processing power and decrease manufacturing costs of integrated circuits. For films thinner than 1.5 nm, high levels of direct tunneling current and reliability problems prevent current SiO2-based dielectrics from being utilized for microprocessor applications. As a result, continual scaling of planar transistor structures demands the introduction of a gate dielectric with a higher permittivity. The premise behind using such a material is to increase the physical thickness of the gate dielectric stack for a given capacitance density, thereby reducing tunneling current.; The replacement candidate for this study was chosen after a thorough investigation of materials and electrical properties for a number of metal oxides. ZrO2 was chosen as it exhibits the proper combination of permittivity and barrier height properties, is thermodynamically stable on silicon, and is able to exhibit an exceptional interface with silicon. An atomic layer deposition (ALD) process was concurrently chosen as a promising method for producing these new high permittivity films.; The microstructure of the Si/SiO2/ZrO2 system was analyzed using a combination of techniques including transmission electron microscopy, electron diffraction and x-ray photoelectron spectroscopy. These techniques, in addition to capacitance and leakage analyses, were further utilized to assess effects of thermal processing in different ambients on gate stack integrity. It is shown that control of oxygen partial pressure after ZrO2 deposition is critical for thermal stability of the gate stack structure.; Compatibility of silicon-based electrodes with the Si/SiO2/ZrO 2 system has been previously reported using a diffusion barrier between ZrO2 and silicon electrode. In this study, we demonstrate that thermal stability can exist under conventional dopant activation conditions without the use of a barrier layer and show how gate stack stability depends on oxygen activity during the silicon electrode growth process.; It is demonstrated that capacitance densities greater than that of 1.5 nm SiO2 films are obtainable using various silicon surfaces preparations. Scaling capabilities of resultant interfacial layers and corresponding ZrO 2 gate stacks were studied. Important electrical properties of these samples and their potential effects on overall transistor performance are discussed.