A fast-locking frequency synthesizer for GSM base-stations in 180nm CMOS.

摘要

GSM Base-stations have extremely stringent phase noise and lock-time specifications due to simultaneous communication with multiple mobile transceivers in a given range. Therefore, they are usually implemented using many off-chip components, especially the VCO. In this work, a 2GHz Dual-Loop-PLL architecture targeting this application is designed, fabricated and tested. A fourth-harmonic mixer is applied in the feedback path of the main loop to significantly reduce the tuning range required of the reference loop. An auxiliary charge pump technique can be used to reduce the capacitance of the loop filter to manageable monolithic values. Alternatively, an analogue of this technique is proposed to widen a given loop bandwidth to enable a fast-lock mode in the PLL.; The main loop employs a bondwire VCO, while the reference PLL contains a spiral-inductor-based VCO. Coarse tuning is utilized to account for process and bondwire inductance variations. The analog and digital power supplies are separated as much as possible to minimize spur feedthrough. The reference PLL and main PLL use crystal frequencies of 2MHz and 50MHz respectively. The synthesizer has been implemented in 180nm CMOS technology, with Chip-on-Board bonding. Open-loop measurements on the bondwire VCO showed an oscillation frequency of 1.55GHz and phase noise values between -121dBc/Hz and -133dBc/Hz 600kHz offset over four test boards. Based on oscillation frequency measurements, the variation in inductance of the bondwires was around 5%. The phase noise value of the spiral VCO on open loop was -113dBc/Hz 600kHz offset. Closed-loop spot phase noise values of -117dBc/Hz 600kHz offset & -145dBc/Hz 20MHz offset were measured on the Main PLL. Similarly, the Reference PLL yielded values of -112dBc/Hz 600kHz & -144dBc/Hz 20MHz offset. The tuning range of the MPLL was 300MHz, while that of the RPLL was 250MHz. The synthesizer consumes a total current of 53mA from a 1.8V power supply.