Design and Implementation of a Co-Processor for Object-Oriented Programming with FPGA

摘要

Object-oriented programming (OOP) is becoming the trend. The current architectures: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC) are showing their inefficiency of running object-oriented programs. Lack of security support is another motiv ation for a new architecture. High Level Instruction Set Computer (HISC) aims at solving these two major disadvantages of the current computer architecture. It is a general-purpose architecture that extends the features of typical descriptor computer architecture to give support in OOP, better security, and multimedia application. From the preliminary simulation result, the HISC speed-up exceeds ten times performance over SPARC on a simple Java program with JIT compiler in a simulation model. This paper discusses the design and implementation of a co-processor based on HISC architecture with Xilinx Virtex XCV 800 FPGAs on a Nallatech Ballynuey Virtex PCI card. The focus is on how we are designing HISC as a co-processor and the integration of the HISC Co-Processor to the PC. Then, with the co-processor system, we can evaluate the performance of HISC.