Routing-efficient implementation of an internal-response-based BIST architecture

摘要

Recently internal-response-based BIST techniques are proposed. By using internal circuit responses to directly generate test patterns, these techniques can significantly reduce or even eliminate storage requirement for test data. For these techniques, appropriate routing of the circuit internal nets to the BIST circuitry is crucial for minimizing the required area overhead and the induced performance impact. In this paper, an efficient net sharing algorithm together with special response decompressor hardware is proposed to minimize the total number of required internal nets for an internal-response-based BIST scheme. Experimental results show that on average 3.24% of nets and 2.83% area overhead of the response decompressors are sufficient to achieve complete fault coverage for ISCAS'85 circuits.