Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan;
CMOS integrated circuits; current-mode logic; frequency dividers; phase locked loops; voltage-controlled oscillators; CMOS; VCO; current mode logic; frequency 10 GHz; frequency divider; gain-boosting design; high speed networking; phase-locked loop circuit; power 18.7 mW; power consumption reduction; size 0.13 mum; true single phase clock logic; voltage 1.2 V; Phase-Locked Loop (PLL); True Single Phase Clock (TSPC); current mode logic (CML); gain boosting;
机译:采用0.13μmCMOS技术的低杂散,低抖动10GHz锁相环
机译:使用0.13-CMOS失调锁相环的低噪声,低功耗频率合成器
机译:采用0.13-μmCMOS的50GHz锁相环
机译:18.7MW 10-GHz锁相环电路在0.13-μmCMOS中
机译:对亚微米CMOS锁相环电路中的相位噪声和抖动的研究。
机译:高速调频原子力显微镜的宽带低延迟锁相环电路设计的定量比较
机译:一种基于自适应延迟锁相环的同步驱动方法,用于拼接CMOS图像传感器