A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13- CMOS

摘要

In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 $mu{rm m}$ CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.