Study of Temperature Sensitivity on Linearity Figures of Merit of Ge/Si Hetero-Junction Gate-Drain Underlapped Vertical Tunnel FET with heterogeneous gate dielectric structure for Improving Device Reliability

著录项

• 来源
  《URSI Regional Conference on Radio Science》|2020年|1-4|共4页
• 会议地点 Varanasi(IN)
• 作者

  Manas Ranjan Tripathy; Ashish Kumar Singh; Kamalaksha Baral; Prince Kumar Singh; Ashwini Kumar Mishra; Deepak Kumar Jarwal; Satyabrata Jit;

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• 作者单位

  Indian Institute of Technology (BHU) Department of Electronics Engineering Varanasi India;

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• 会议组织
• 原文格式 PDF
• 正文语种
• 中图分类
• 关键词

  TFET; heterojunction; heterogenous gate dielectric; sub-threshold swing (SS); source pocket; drain underlap; linearity; FOMs;

  机译：TFET;异质结异质栅电介质亚阈值摆动（SS）;源袋;排水漏斗线性FOMs;