Low Voltage and High Speed Silicon Nanocrystal Memories

摘要

We have studied a set of MOS cell structures with 30 nm thick thermal oxide implanted with Si at high doses (10, 15 and 20 atomic % at projected range) in which Si nanocrystals (Si-nc) have been precipitated by annealing at 1100℃. Energy filtered transmission electron microscopy reveals: ⅰ) a central layer of Si-nc with a mean size of 2.8 nm; ⅱ) a control oxide of 12.5 nm completely free of Si-nc and ⅲ) a tunnel oxide of about 2.5 nm. This narrow tunnel oxide enables the direct tunnel for charging and discharging which is a must for high speed and good reliability. However, this results in typical retention times ranging from only few hours to several months, depending on the concentration of Si-nc. For developing low voltage memories we have focused on the highest Si excess sample, which shows fast write times (tens of μs) at very low gate fields (± 2 MV/cm or ± 6V). The onset of Fowler-Nordheim conduction is of about ± 6 MV/cm by J-V measurements (± 18V), which means that the structure works in a direct tunnel regime. To increase the retention time we have performed an additional annealing step in diluted O_2 for 16 and 32 minutes, resulting in a dramatic increase in the retention times, which is attributed to the re-growth of an additional tunnel oxide which eliminates surface roughness, remaining Si excess and defects at the Si-SiO_2 interface. This additional oxidation step produces also a decrease in the mean size of the Si-nc distribution. Thus, we increase the retention time beyond the 10 years standard limit. Finally, the writing times can be traded-off by increasing slightly the program voltage up to ± 2.7 MV/cm or ± 8V.