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Low-temperatue PECVD SiO_2 on Si and SiC

机译:Si和SiC上的低温PECVD SiO2

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摘要

The deposition of SiO_2 films by plasma-enhanced-chemical-vapor-deposition (PECVD) using tetraetylorthosilicate (TEOS) was studied. MOS capacitors were fabricated on both Si and SiC for this study. Several different sets of experiments were conducted for PECVD deposition according to different growth parameters and the results compared. For Si samples with SiO_2 deposited at a substrate temperature 300 deg C, the C approx V curve gave a flat-band voltage of 1V and a transition slope of 112 pF/V. The dielectric constant of te depositied SiO_2 film was 4.2 and the si/SiO_2 interface trap density was calculated to be 1.8x10~(10) cm~(-2). The I-V curve showed a leakage current density of 1.210~(-9) a/cm~2 and dielectric breakdown field strength of 9.2 MV/cm. For SiC samples, the PECVD deposition gave a uniform SiO_2 film with a controllable deposition rate of 0.3nm/sec. The refractive index and dielectric constant of the as-deposited SiO_2 film were 1.46 and 3.84 respectively. The I approx V curve showed a leakage current density of 2x10~(-9) a/cm~2 and a breakdown field of 4.7 MV/cm.
机译:研究了使用原硅酸四乙酯(TEOS)通过等离子体化学气相沉积(PECVD)沉积SiO_2薄膜的方法。为了进行这项研究,在Si和SiC上都制造了MOS电容器。根据不同的生长参数对PECVD沉积进行了几组不同的实验,并比较了结果。对于在衬底温度为300摄氏度下沉积SiO_2的Si样品,C近似V曲线给出的平带电压为1V,跃迁斜率为112 pF / V。沉积的SiO_2薄膜的介电常数为4.2,计算得出的si / SiO_2界面陷阱密度为1.8x10〜(10)cm〜(-2)。 I-V曲线的漏电流密度为1.210〜(-9)a / cm〜2,介电击穿场强为9.2 MV / cm。对于SiC样品,PECVD沉积得到均匀的SiO_2膜,可控制的沉积速率为0.3nm / sec。所沉积的SiO 2膜的折射率和介电常数分别为1.46和3.84。 I近似V曲线显示泄漏电流密度为2x10〜(-9)a / cm〜2,击穿电场为4.7 MV / cm。

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