首页> 外文会议>Symposium on Gate Stack and Silicide Issues in Silicon Processing II, Apr 17-19, 2001, San Francisco, California >Engineered tantalum aluminate and hafnium aluminale ALD films for ultrathin dielectric films with improved electrical and thermal properties
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Engineered tantalum aluminate and hafnium aluminale ALD films for ultrathin dielectric films with improved electrical and thermal properties

机译:工程铝酸钽和铝aALD膜用于超薄介电膜,具有改善的电学和热学性能

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Continued scaling of device dimensions requires deposition of high-quality thin films with a thickness of 50 angstroms or less. Nucleation effects in typical CVD processes make it difficult to achieve continuous films in this thickness regime. Atomic layer deposition (ALD), a technique developed over 25 years ago but applied to IC processing only recently, enables deposition of ultra-thin films with atomic-scale precision. This technique offers 100 percent step coverage of high aspect ratio features, as-deposited films which are amorphous and free of pinholes, excellent within-wafer uniformity and wafer-to-wafer uniformity, and favorable electrical properties. Moreover, ALD offers the opportunity to engineer material properties by creating layered structures (nanolaminates) and mixtures (alloys) which combine advantageous properties of different materials. These last features may be critical in efforts to replace silicon dioxide as the industry's dielectric workhorse if no single material emerges as a suitable direct replacement. The nanolaminate capability of ALD will be discussed with physical and electrical data on nanolaminates of aluminum oxide with tantalum pentoxide and aluminum oxide with hafnium oxide. Individual nanolaminate layers can be varied from tens of angstroms to as little as 1-2 atomic layers. Data for Al_2O_3/Ta_2O_5 and Al_2O_3/HfO_2 alloys will also be presented demonstrating the ability to create materials with controlled, variable composition. The alloy and nanolaminate capabilities enable the creation of graded interfaces and atomically smooth transitions between different materials. Prospects for application of these materials to gate stacks and capacitors will be assessed.
机译:器件尺寸的持续缩小需要沉积厚度为50埃或更小的高质量薄膜。典型的CVD工艺中的成核作用使得很难在这种厚度范围内获得连续的膜。原子层沉积(ALD)是25年前开发的技术,但直到最近才应用于IC处理,它能够以原子级的精度沉积超薄膜。该技术可提供100%的高纵横比特征的阶梯覆盖率,非晶态且无针孔的沉积薄膜,极好的晶圆内均匀性和晶圆间均匀性以及良好的电性能。此外,ALD提供了通过结合不同材料的有利性能的分层结构(纳米复合材料)和混合物(合金)来设计材料性能的机会。如果没有一种材料可以作为合适的直接替代品,那么这些最后的特性对于替代二氧化硅作为行业的电介质工作至关重要。将通过物理和电学数据讨论氧化铝与五氧化钽和氧化铝与氧化ha的纳米叠层的ALD纳米叠层能力。各个纳米层的厚度可以从几十埃到低至1-2个原子层不等。也将提供Al_2O_3 / Ta_2O_5和Al_2O_3 / HfO_2合金的数据,证明其具有制造具有受控,可变组成的材料的能力。合金和纳米层压板的功能可创建渐变界面,并在不同材料之间实现原子平滑过渡。将评估将这些材料应用于栅极叠层和电容器的前景。

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