Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

机译：电源/信号线与SRAM电路在65nm CMOS电感耦合链路中的干扰

获取原文

页面导航

摘要
著录项
引文网络
相似文献
相关主题

摘要

This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is smaller th

机译：本文讨论了65nm CMOS中电感耦合链路的干扰。模拟和测量了从电源/信号线到SRAM的电磁干扰。电力线对移动应用（线路和空间）的干扰较小

著录项

来源
《Solid-State Circuits Conference, 2007 IEEE Asian》|2007年|P.131-134|共4页
会议地点 Jeju CityKorea (South)
作者
Niitsu; K.; Sugimori; Y.; Kohama; Y.; Osada; K.; Irie; N.; Ishikuro; H.; Kuroda; T.;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类
关键词
CMOS memory circuits; SRAM chips; electromagnetic interference; logic circuits; CMOS inductive-coupling link; SRAM circuits; electromagnetic interference; logic circuits; mobile applications; power lines interference; signal lines interference; size 65 nm; transmit;

机译：CMOS存储电路； SRAM芯片；电磁干扰;逻辑电路； CMOS电感耦合链路； SRAM电路；电磁干扰;逻辑电路；移动应用程序；电力线干扰；信号线干扰；尺寸65 nm;发送;

相似文献

外文文献
中文文献
专利

1. Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration [J] . Niitsu K., Sugimori Y., Kohama Y., Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2011,第10期

机译：用于低功耗3D系统集成的CMOS电感耦合链路中缓解电源/信号线和SRAM电路干扰的分析和技术
2. Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link [J] . Kiichi NIITSU, Noriyuki MIURA, Mari INOUE, IEICE Transactions on Electronics . 2007,第4期

机译：菊花链发送器，用于降低电感耦合CMOS链路的功耗
3. An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology [J] . SHAN Weiwei, WANG Xuexiang, LIU Xinning, 电子学报：英文版 . 2014,第004期

机译：65nm CMOS技术中的超低稳态电流电流正电阻
4. Interference from Power/Signal Lines and to SRAM Circuits in 65nm CMOS Inductive-Coupling Link [C] . Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, IEEE Asian Solid-State Circuits Conference . 2007

机译：从电源/信号线和65nm CMOS电感耦合链路中的SRAM电路干扰
5. W-band front-end integrated circuits in 65nm CMOS technology. [D] . Khanpour, Mehdi. 2008

机译：采用65nm CMOS技术的W波段前端集成电路。
6. Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits [O] . Yiming Li, Chieh-Yang Chen, Min-Hui Chuang, 2019

机译：随机纳米氮化钛晶粒引起的动态功率延迟的特性波动以及全能门纳米线CMOS器件和电路的纵横比效应
7. An FSK Inductive-Coupling Transceiver Using 60mV 0.64fJ/bit 0.0016mm2 Load-Modulated Transmitter and LC-Oscillator-Based Receiver in 65nm CMOS for Energy-Budget-Unbalanced Application [O] . Kenya HAYASHI, Shigeki ARATA, Ge XU, 2019

机译：FSK电感耦合收发器使用60mV 0.64fj / bit 0.0016mm 2 负载调制的发射器和基于LC-振荡器的接收器，用于65nm CMOS的能量预算不平衡应用

Interference from power/signal lines and to SRAM circuits in 65nm CMOS inductive-coupling link

摘要

著录项

引文网络

相似文献

相关主题

期刊订阅