Polishing of copper integrated with dielectric films of k < 2.8: Challenges and Solutions

摘要

This talk will be addressed to highlight the primary challenges encountered in utilizing multi-level copper CMP in the integration and copper metallization of integrated circuits based on current needs and demands in the IC industry. CMP has become a mainstream-processing module in the IC industry a few years ago. Dielectric (undoped glass) CMP and Tungsten CMP have been used in manufacturing worldwide for the past several years. Copper CMP still remains more in the research and development mode rather than the manufacturing mode. There are multiple reasons for copper polishing not becoming mainstream in manufacturing fast enough. Interestingly, the knowledge-base that has been built up from the research community, development community and manufacturing community in the areas of dielectric and tungsten CMP will be of help in the implementation of multi-layer copper CMP. Also, the challenges of copper CMP gets more enhanced by the choice of the dielectric. The recent preferred dielectrics for obvious reasons have been the ones with lowest dielectric constant. In this talk, we will limit the discussion to dielectrics of values around k～2.8.