Characterization of traps in scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

摘要

At the ITRS 45nm technology node, NMOS transistors with high-K dielectrics have an effective oxide thickness (EOT) less than 1nm. An increase in trap density, both at the interface and in the film, is observed as a result of the incorporation of high-K materials into these devices. In our research, several experimental methods have been used to study these on scaled NMOS transistors — devices with ultra-thin high-k dielectric layer and metal gate. These methods include 1/f noise characterization, charge pumping and subthreshold region characterization.