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High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor
High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor
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机译:高K金属栅极工艺可降低NMOS晶体管中的结泄漏和界面陷阱
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摘要
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.
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