Low Power Input/Output Port Design Using Clock Gating Technique

摘要

Clock gating is a well-known technique to reduce chip dynamic power. This paper propose a modified clock gating techniques based on ACG(Adaptive Clock Gating) and instruction level clock gating. The proposed clock gating technique reduces not only switching activity of functional blocks in IDLE state but also dynamic power in running state. Our modified ACG can automatically enable or disable the clock of the functional block. The experimental results on some I/O port core in SoC show an average of 19.45% dynamic power reduction comparing to previous ACG technique.