Design of Coarse Grained Architecture with Gated Clock Technique for Low Power Applications

摘要

In recent times, reconfiguration system is widely used due to their combination of efficiency and flexibility. Hardware based reconfiguration offers to use the same hardware for the different purpose of the optimized hardware utilization. Coarse grained (CGRA) and fine grained (FGRA)are the two types of reconfigurable architectures used in the present time. In the CGRA, the hardware functionality is specified at the word level. Likewise, the FGRA, hardware functionality is specified at a bit level. Coarse grained reconfigurable architecture (CGRA) needs many processingelements (PEs) and configuration memory for reconfiguration operation. CGRA reconfigure the processing element from one process to another process dynamically without any performance degradation. The CGRA system is designed with 16 processing elements; it’s arranged in a 4×4 matrixstructure. Each processing elements are configured by more than one operation. The operation can be selected and changed by using the selection bits. According to the selection bit, the operation of the processing element is changed; likewise, reconfiguration bit is used to reconfigure theprocessing elements. Although the reconfiguration architecture provides higher performance and flexibility, it consumes a significant amount of power. Reducing power in the CGRA and FGRA is the very critical issue; avoid this kind of situation by proposed the clock gating and pipelining reusetechniques. The proposed techniques avoid the unwanted usage of the clock signal during the operation of processing elements. Interconnections between the processing elements are essential in the CGRA structure. The proposed architecture was simulated by Modelsim 6.3c, synthesized and analyzedby Xilinx ISE simulator and Quartus with cyclone II device.