CODA: Coarse Grain Dataflow Architecture: Integration of a Parallel Architecture and RISC-

摘要

Mitigating the synchronization cost and utilizing the locality of storage references are key issues of parallel processing. Parallel architectures currently presented are referred to in these terms. The discussion emphasizes the importance of synchronization on a fast storage element where the locality is utilized efficiently. Synchronization on a slow storage element degrades the locality utilization and machine performance. CODA enables synchronization on a register by using the instruction insertion which inserts the packet-transformed-instruction(s) into a normal instruction stream. Thus, computation and communication are integrated on a simple execution pipeline. With the instruction insertion, a CODA prototype processor chip succeeds in incorporating RISC into a parallel architecture. CODA efficiently supports the prefetch of a remote datum. As for the loop control structure, the prefetch oriented code, which copes with the delay of a remote storage access, is obtained by a simple transformation technique.