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Mixed style of Low Power Multiplexer Design for Arithmetic Architectures using 90nm Technology

机译:使用90nm技术的用于算术架构的低功耗多路复用器设计的混合样式

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As many researches are concentrating more on arithmetic circuits particularly with Multiplexer (MUX) design as heart of them, this paper also deals with MUX to optimize the power and hence the overall architecture of any greater module may have the considerable reduction in power. The combination of pass transistor (transmission gate) + static method gives a mixed style of MUX which is proposed in this paper and ensures full swing over pass transistor (alone) type of implementation. The circuit swing is an important factor because the use of 2-1 MUXes in a de-composed multiplexer must propagate the data to the output without signal degradation. TSPICE is the circuit simulator tool used and 90nm library is included for simulation. The power analysis and comparison between Complementary Static CMOS, Pass Transistor and the proposed styles will conclude this work is a better approach.
机译:由于许多研究更多地集中在算术电路上,尤其是以复用器(MUX)设计为核心,因此本文还涉及MUX以优化功耗,因此,任何更大模块的整体架构都可能会大幅降低功耗。传输晶体管(传输门)+静态方法的组合给出了本文中提出的MUX的混合样式,并确保了完整的摆幅式传输晶体管(单独)类型的实现。电路摆幅是一个重要因素,因为在分解后的多路复用器中使用2-1 MUX必须将数据传播到输出而不会降低信号。 TSPICE是使用的电路仿真器工具,并且包含90nm库用于仿真。通过对互补静态CMOS,传输晶体管和所提出的样式进行功率分析和比较,可以得出结论,这项工作是更好的方法。

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