首页> 外文会议>Recent advances in networking, VLSI and Signal processing >A SURVEY OF LOW POWER HIGH SPEED ONE BIT FULL ADDER
【24h】

A SURVEY OF LOW POWER HIGH SPEED ONE BIT FULL ADDER

机译:低功耗高速一位全量程调查

获取原文
获取原文并翻译 | 示例

摘要

In this paper, a structured approach for analyzing the adder design is introduced. Analysis is based on some simulation parameter like No. of transistors, power, delay, power delay product, different technologies, aspect ratio. Each reference used different tool for the simulation purpose. The different circuit design are studied and evaluated extensively. Several designs give a different designing approach and give a new information which can relate with different application. Each of these circuits cell exhibits different power consumption, delay and area in different VLSI technology. This paper can be said as a library of different full adder circuits that will be beneficial for the circuit designers to pick the full adder cell that satisfied their specific application.
机译:本文介绍了一种用于分析加法器设计的结构化方法。分析基于一些仿真参数,例如晶体管数量,功率,延迟,功率延迟乘积,不同技术,纵横比。每个参考都使用不同的工具进行仿真。对不同的电路设计进行了广泛的研究和评估。几种设计给出了不同的设计方法,并给出了可以与不同应用程序相关的新信息。在不同的VLSI技术中,这些电路单元中的每一个都表现出不同的功耗,延迟和面积。可以说本文是一个包含不同全加法器电路的库,这将有助于电路设计人员选择满足其特定应用的全加法器单元。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号